In addition to transistors, components such as capacitors and inductors can be formed on either semiconducting or conventional substrates. In these types of devices, a dielectric film must be patterned on the substrate in order to isolate the capacitor/inductor and minimize stray capacitance. In the case of alumina ceramic (Al.sub.2 O.sub.3) conventional dielectric materials are used and are patterned using conventional wet and dry etch methodology. Similar methods are also used in the case of semiconducting substrates such as silicon and gallium arsenide (GaAs). It is highly desirable to have a dielectric film that has a high dielectric constant (K), since devices can then be made smaller and will have a wider range of values. However, the highly crystalline nature of high K dielectrics (and also ferroelectric and magnetic oxides) dictates that conventional etching methods such as chemical etching and wet etching are not especially useful. Crystalline materials are highly structured and very resistant to chemical and gaseous etchants. Thus, the use of high K crystalline dielectrics has been extremely limited in the art, and practitioners have been forced to limit themselves to non-crystalline, i.e., amorphous (example, SiO.sub.2), materials that have a significantly lower dielectric constant. Because of their non-structured nature, amorphous films are significantly easier to etch, both chemically and using plasma etch, and have found favor in the industry.
It would be highly desirable if a method could be devised to use conventional patterning and etching techniques in order to create high K capacitors and inductors.